1. Field of the Invention
The present invention relates generally to random access memories (hereinafter referred to as RAMs) and, more particularly, to a precharge system of input/output lines in an RAM including a memory array divided into a plurality of memory array portions.
2. Description of the Background Art
In recent years, an RAM having a memory array divided into a plurality of memory array portions has been employed in general. FIG. 1 is a diagram schematically showing structure of a conventional MOS dynamic RAM as one example of the RAM thus structured. With reference to FIG. 1, a plurality of memory array portions 2-1, 2-2, . . . , 2-n constituting a single memory array as a whole are formed on a semiconductor chip 1. Sense amplifier portions 3-1, 3-2, . . . , 3-n are formed corresponding to respective memory array portions 2-1, 2-2, . . . , 2-n.
A plurality of CSL (column select line) lines extend from a column decoder 4 through the plurality of memory array portions and the plurality of sense amplifier portion to correspond to respective columns of memory cells constituting the memory array. Column decoder 4 activates one of the plurality of CSL lines, which corresponds to a Y address of a memory cell from which data is to be read, in response to a column (Y) address signal applied from an external address signal source not shown.
A plurality of word lines (WL) extend from a row decoder 5 into their corresponding memory array portions to correspond to respective rows of memory cells constituting the memory array. Row decoder 5 responds to a row (X) address signal applied from an external address signal source not shown to activate one of the plurality of word line, which corresponds to an X address of a memory cell from which data is to be read.
Data read from a single memory cell which is included in any of the memory array portions and specified by those X and Y addresses is applied via a bit line pair not shown to one of sense amplifier portions 3-1, 3-2, . . . , 3-n, which corresponds to the above memory array portion. The applied data is amplified in the corresponding sense amplifier portion and then output to the outside via a corresponding I/O line (data line) pair.
FIG. 2 is a partially enlarged diagram showing a part relating to a certain CSL line, of the entire structure of the dynamic RAM shown in FIG. 1. That is, with reference to FIG. 2, each of the plurality of CSL lines extending from column decoder 4 extends through memory array portions 2-1, 2-2, . . . , 2-n and are connected in common to control inputs of gates 6-1, 6-2, . . . , 6-n corresponding to the respective memory array portions.
A single column which is constituted by a plurality of memory cells (not shown) and provided in each memory array portion (e.g., 2-1) with respect to the single CSL line is connected to a pair of bit lines (BL, BL). This bit line pair is connected through a sense amplifier SA (e.g., 3-1) and a gate (e.g., 6-1) corresponding to each memory array portion to a pair of I/O lines (I/O, I/O) corresponding to each memory array portion. Bit line precharge circuits 7-1, 7-2, . . . , 7-n for precharging the above-described bit line pairs (BL, BL) are provided corresponding to the respective bit line pairs.
Signals on the I/O line pairs are amplified, respectively, by preamplifiers 9-1, 9-2, . . . , 9-n and then output to the outside. I/O line precharge circuits 8-1, 8-2, . . . , 8-n for precharging the above-described I/O line pairs (I/O, I/O) are provided. It is assumed that with respect also to each of the remaining CSL lines not shown in FIG. 2, the circuits of the same structure as in FIG. 2 are formed.
FIG. 3 is a circuit diagram showing in detail parts relating to first and second memory array portions 2-1 and 2-2 in FIG. 2. A description will now be given on the structure and operation of the first memory array portion 2-1 shown in FIG. 3 and each circuit relating to the first memory array portion.
While memory array portion 2-1 inherently includes a plurality of memory cells arranged two-dimensionally in rows and columns, only one memory cell MC to be accessed is shown in FIG. 3 for facilitating the description. This memory cell MC is provided at a crossing point of a corresponding word line WL and a corresponding bit line BL.
A bit line pair 11-1 constituted by bit lines BL1 and BL1 is connected through sense amplifier 3-1, bit line precharge circuit 7-1 and gate 6-1 to a corresponding I/O line pair 10-1. Bit line precharge circuit 7-1 includes transistors Q1, Q2 and Q3 which are turned on/off in response to a clock signal BLP1 applied from an internal signal generating source not shown. When those transistors are turned on in response to clock signal BLP1, bit line pair 11-1 is connected via transistors Q1 and Q2 to a precharge voltage source and is further equalized by transistor Q3. As a result, bit lines BL1 and BL1 are respectively precharged to a bit line precharge voltage V.sub.BL. This precharge voltage V.sub.BL is normally set to a half (1/2) of a supply voltage V.sub.CC.
Gate circuit 6-1 includes transistors Q4 and Q5 which are turned on/off in response to a potential on the CSL line extending from column decoder 4. When those transistors are turned on in response to the potential on the CSL line, bit line pair 11-1 is connected via transistors Q4 and Q5 to I/O line pair 10-1.
I/O line pair 10-1 is connected to its corresponding preamplifier 9-1, and this I/O line pair is connected with an equalizing transistor Q6 and I/O line precharge circuit 8-1 in its course. I/O line precharge circuit 8-1 includes transistors Q7 and Q8 which are turned on/off in response to a clock signal IOPC applied from an internal signal generating source not shown. When those transistors are turned on in response to clock signal IOPC, I/O line pair 10-1 is connected via transistors Q7 and Q8 to the above-described precharge voltage source, and I/O line pair (I/O, I/O) is precharged to the above-described precharge voltage V.sub.BL. This I/O line pair 10-1 is equalized by transistor Q6 which is turned on/off in response to an equalizing signal EQ applied from an internal signal generating source not shown. The same structure as above is also applied to other memory array portions and their circuits relating thereto.
A description will now be made on an operation of the circuitry of FIG. 3 in a case where a request for access is actually made. The following description is about a case where first memory array portion 2-1 shown in FIG. 3 is accessed, whereas second memory array portion 2-2 is not accessed.
First, in a standby period, a potential on the CSL line of FIG. 3 is at a logic low level, and each bit line pair and each I/O line pair are separated from each other by a gate circuit in any of the memory array portions. Each precharge circuit is activated in response to each type of clock signals, and all the bit line pairs and I/O line pairs are precharged to the above-described precharge voltage V.sub.BL =1/2.multidot.V.sub.CC.
When first memory array portion 2-1 is accessed, each of the above clock signals BLP1 and IOPC and equalizing signal EQ attains a logic low level, so that transistors Q1, Q2, Q3, Q6, Q7 and Q8 are turned off. Consequently, both bit line pair 11-1 and I/O line pair 10-1 are separated from precharge voltage source V.sub.BL and maintain their respective precharged potentials intactly.
When a potential on word line WL corresponding to memory cell MC from which data is to be read rises, the data stored in the memory cell is read out onto a bit line BL, and a potential difference occurs between paired bit lines BL1 and BL1. The potential difference is amplified by sense amplifier 3-1. The potential on the corresponding CSL line is subsequently raised to a logic high level by column decoder 4, so that transistors Q4 and Q5 constituting gate 6-1 are turned on. As a result, the data on the bit line pair is transferred via gate 6-1 onto I/O line pair 10-1. The transferred data is then amplified by preamplifier 9-1 and then output to the outside.
In second memory array portion 2-2, clock signals BLP2 and IOPC are at a logic high level, and precharge circuits 7-2 and 8-2 remain activated. That is, both of the potentials on bit line pair 11-2 and I/O line pair 10-2 are kept at V.sub.BL =1/2.multidot.V.sub.CC.
Now, if the potential on the CSL line is raised to a logic high level by column decoder 4 as described above, then transistors Q14 and Q15 constituting gate 6-2 are turned on concurrently with the foregoing transistors Q4 and Q5, so that bit line pair 11-2 and I/O line pair 10-2 are connected to each other. Since the potential on bit line pair 11-2 and that on I/O line pair 10-2 are originally the same potential, the respective potentials on bit line pair 11-2 and I/O line pair 10-2 are kept at V.sub.BL =1/2.multidot.V.sub.CC intactly even after gate 6-2 is opened as described above.
As mentioned above, in such an RAM that employs a system (CSL system) in which each connection of a bit line pair and I/O line pair is controlled in common by a signal on a single CSL line of column decoder 4 in both of the memory array portion (e.g., 2-1 of FIG. 3) to be activated and the memory array portion (e.g., 2-2 of FIG. 3) not activated, bit line pair 11-2 and I/O line pair 10-2 are short-circuited in access time also in the inactivated memory array portion (2-2). Accordingly, if a precharge level of the bit line pair is different from that of the I/O line pair, a current flows between the bit line pair and the I/O line pair in accordance with the rising of the potential on the CSL line also in the memory array portion not to be accessed, resulting in an increase in consumption of currents.
Thus, in the conventional RAM, the precharge level of the bit line pair and that of the I/O line pair are set to the same level (1/2.multidot.V.sub.CC), thereby preventing such unnecessary consumption of currents. As described above, such an approach that the precharge level of the I/O line pair is set to the level of 1/2.multidot.V.sub.CC like the precharge level of the bit line pair in the RAM of the CSL system is disclosed in, for example, "An Experimental 1 Mb DRAM with On-Chip Voltage Limiter" by K. Itoh et al. on page 282 of Digest of Technical Papers of 1984 IEEE International Solid-State Circuits Conference.
However, setting the precharge level of the bit line pair and that of the I/O line pair independently to different potentials results in the following merits.
FIG. 4 is a timing chart showing changes in logic level of a bit line pair in the case where a sense amplifier is activated for data reading from memory cell MC; and FIG. 5 is a timing chart showing changes in a logic level of an I/O line pair which has received data from the bit line pair. A description will now be made on merits provided when the respective precharge levels of the bit line pair and the I/O line pair are set to independently different potentials with reference to FIGS. 4 and 5.
First, if a potential on a word line WL (FIG. 4(a)) rises to a level not lower than V.sub.CC and word line WL is activated, then charges in a memory cell MC connected to this word line WL are read out onto one bit line BL of the bit line pair. In a case where memory cell MC in memory array portion 2-1 of FIG. 3 has stored data of a logic low level, for example, a potential on bit line BL1 changes by .DELTA.V.sub.L as shown in FIG. 4(b), while a potential on the other bit line BL1 does not change.
Then, the logic level of bit line BL1 is lowered to a ground potential GND by sense amplifier 3-1, so that the level difference .DELTA.V.sub.L is amplified (time t.sub.1). The logic level of bit line BL1 is subsequently restored to supply potential V.sub.CC by sense amplifier 3-1 (time t.sub.2). The reason why a discharge from bit line BL1 of the logic low level is carried out in advance is as follows. That is, assuming an n channel transistor and a p channel transistor having the same dimension, since mobility of electrons is greater than that of holes, the n channel transistor employing electrons as carriers switches at a higher switch speed than the p channel transistor employing holes as carriers and hence it can operate faster.
The data amplified by sense amplifier 3-1, as shown in FIG. 4(b), is transmitted onto I/O line pair 10-1 when gate 6-1 is opened in response to a CSL output of column decoder 4. Then, the potential on this I/O line pair is amplified by a self-amplifying action of sense amplifier 3-1.
FIG. 5(a) indicates a speed of amplification of a potential difference between a pair of I/O lines when the precharge level of the I/O line pair is set to the level of V.sub.CC -V.sub.th higher than the level of 1/2.multidot.V.sub.CC ; and FIG. 5(b) indicates a speed of amplification of a potential difference between the pair of I/O lines when the precharge level of the I/O line pair is the level of 1/2.multidot.V.sub.CC. In comparison between (a) and (b) in FIG. 5, with respect to time required when the potential difference between the paired I/O lines is amplified up to 200 mV, time t.sub.3 in the case where the precharge level of the I/O line pair is V.sub.CC -V.sub.th is shorter than time t.sub.4 in the case where the precharge level is 1/2.multidot.V.sub.CC. That is, since discharge is carried out at a higher speed via the n channel transistor of sense amplifier 3-1 in the case with the higher precharge level of the I/O line pair, the potential difference between the paired I/O lines is amplified at a higher speed. This leads to a conclusion that the case with the higher precharge level of the I/O line pair is more advantageous than the case with the lower precharge level.
As mentioned above, in order to achieve a faster data reading operation of the RAM, it is desirable that the precharge level of the I/O line pair is set to the level of V.sub.CC -V.sub.th higher than 1/2.multidot.V.sub.CC which is the precharge level of the bit line pair. Furthermore, if the precharge levels of both I/O line pair and bit line pair are set to 1/2.multidot.V.sub.CC, the load imposed on a 1/2.multidot.V.sub.CC voltage generating circuit will be increased. In such a case, there is a possibility that the I/O line pair may not be precharged sufficiently if the equalizing time period is relatively short. If the capability of the 1/2.multidot.V.sub.CC voltage generating circuit is enhanced, on the other hand, there is a problem of the increase of currents consumed by generating circuit itself. Accordingly, in order to reduce load imposed on a 1/2.multidot.V.sub.CC voltage generating circuit, it is desirable that the level of V.sub.CC -V.sub.th which can be easily generated is employed as the precharge level of the I/O line pair.
However, if the precharge level of the I/O line pair is set independently of that of the bit line pair, there arises a problem that an unnecessary current flows through the inactive memory array portion unaccessed and thus consumption of currents increases, as described above.
In addition, in order to eliminate such a problem as increased consumption of currents, such structure is considered, unlike the CSL system shown in FIGS. 1-3, that column decoders are provided corresponding, respectively, to a plurality of memory array portions 2-1, 2-2, . . . , 2-n, so as to avoid short-circuits between the bit line pair and the I/O line pair in the unaccessed inactive memory array portion. There is a disadvantage, however, that if a column decoder is provided for each memory array portion, a chip area is substantially increased.